The ongoing progress in the semiconductor industry is continuing to lead to greater device miniaturization. Device miniaturization is enabled by increasing structure pattern density and enhancing functionality that effectively reduces the cost per chip. As the geometric limits of the semiconductor structures are pushed against process technology limits, the dimensions of the structures formed in an integrated circuit have shrunk to the point where tighter tolerances and precise process controls are critical to further device miniaturization and fabrication success.
However, with smaller geometries, precise dimension control has become increasingly difficult. For interconnect via fabrication, many processes are inadequate to produce the needed smaller geometries and the required structural integrity. It is undesirable to have tapered profiles forming at the top and/or sidewalls of the interconnect vias, as such profiles may cause undesirable deviation from electrical property design specifications and thereby compromise the quality and reliability of the semiconductor device. The conventional approach to reduce the dimensions of semiconductor devices is to rely on improvements to the lithographic process. Such improvements can be time consuming and expensive, often requiring additional process steps and/or expensive new equipment.
It is, therefore, desirable to provide a method that has improved process control for fabricating structures with smaller dimensions, in particular, back-end-of-line interconnects.